Data transfer system for transferring data from a computer to a tape device

ABSTRACT

A data transfer system for transferring data between a computer and a video recorder/player is disclosed. Generating means generate a video signal. Coding means code data received from a computer. Mixing means mix the coded data with the video signal to carry the data on the video signal. Furthermore, separating means separate coded data from a video signal received from a video recorder/player. Decoding means decode data separated by the separating means. Settable timing means control the rate of transfer of data between the computer and the video recorder/player. A predetermined number of data bits carried on the video signal are carried on each of a plurality of lines of the video signal. Each line carries markers to define the beginning and end of the line and when the video signal is decoded, missing data bits on a line are replaced by a predetermined sequence of bits, and each such sequence of bits is detected by an error detector and reconstituted by the original bits by an error correction process.

BACKGROUND OF INVENTION

This invention relates to data backup, and is concerned particularlyalthough not exclusively with the backup of data from a computer onto atape.

Personal computers (PCs) are increasingly used in a wide range ofapplications. Such is the widespread use of personal computers that manyhomes are now equipped with a personal computer for word processing,managing personal finances, playing games, education and work relatedtopics. This has inevitably required computers to hold large amounts ofinformation and programs. Early machines had limited hard disk capacity,typically 50 megabytes or less. However, hard disk capacities of 500megabytes are commonplace for newer machines. This poses a problem forthe owner of either the old or new type of machine. The problem with theold machine is how to store more data, and for the new machine how toensure that data is not lost. The hard disk is one of only a fewmechanical components within a modern computer, and as such it issusceptible to wear which can cause data errors. An additional problemis that of software viruses that attack data structures with the outcomebeing data loss.

One solution to both problems is to use a tape backup unit. This wouldallow important files to be duplicated so as to ensure that a copy canbe held in a safe place. Also, less frequently used files could bearchived onto tape, which would free valuable disk space for additionalfiles. Such tape backup disks exist, but are too expensive for many homeusers. A more economical method of data backup is required.

Most homes are equipped with video recorder equipment. Video recordershave been available for some time and are available in many differentforms with varied signal characteristics. These machines were designedto record picture information which by its nature can accommodate manyerrors that would not be perceptible to a viewer. A video recorder canbe used to store information other than pictures. However theinformation must first be converted into a form that the recorderaccepts, a video signal.

It is possible to produce an interface for connecting a video recorderto a PC. Such a system would allow the user to back up information,thereby guarding against loss and allowing space to be freed up forstorage of new information. Systems of this type have been proposed.However, they tend to be expensive and suffer from poor performance, dueto varying capabilities of video recorders and tape media, and varyingdegrees of wear in video mechanisms.

The widespread use of inexpensive video backup systems has been limitedby the varied specification of PCs relating to disk capacity, disk I/Obandwidth, system memory and processor speed, compounded by the varyingcapability of a domestic video recorder in terms of bandwidth anderrors.

SUMMARY OF THE INVENTION

Preferred embodiments of the present invention aim to provide improvedsystems that can overcome the vagaries of differing PC specificationsand video recorder capabilities. Another aim of preferred embodiments ofthis invention is to provide a programmable system that can be switchedbetween several configurations.

Preferred embodiments of the invention aim to calculate the bestpossible conditions for each machine/tape combination and automaticallymodify a data rate, error correction and/or coding scheme accordingly. Afurther aim is to be able to compensate for differing PC specifications,by arranging data into frames whereby missing data can be identified andreplaced with dummy data which is subsequently passed to an errorcorrection process. A further aim is to divide the task of dataencoding/decoding and error correction between a PC microprocessor andthe data processing capabilities of an interface card, in order toachieve the lowest cost implementation of the back up system. A furtheraim is to provide the user with information allowing rapididentification and recovery of selected files.

More generally, according to one aspect of the present invention, thereis provided a data transfer system for transferring data between acomputer and a video recorder/player, the system comprising:

generating means for generating a video signal;

coding means for coding data received from a computer;

mixing means for mixing such coded data with said video signal to carrysaid data on said video signal;

separating means for separating coded data from a video signal receivedfrom a video recorder/player;

decoding means for decoding data separated by said separating means; and

settable timing means for controlling the rate of transfer of databetween a computer and a video recorder/player.

Preferably, at least part of said generating means, coding means, mixingmeans, separating means, decoding means and timing means are embodied asan interface device for cooperation with a computer.

Preferably, said interface device comprises a PC expansion card.

A system as above may include first ranging means for assessing datatransfer rate and associated error characteristics of a videorecorder/player, and providing a control signal or data to said timingmeans.

A system as above may include second ranging means for assessing datatransfer rate and associated error characteristics of a computer, andproviding a control signal or data to said timing means.

Preferably, said second ranging means is arranged to assess CPUperformance, available static memory, disk capacity and disk I/Obandwidth of a computer.

Preferably, at least part of said first and/or second ranging means isembodied by way of a program within said computer.

Preferably, for the data carried on said video signal, a predeterminednumber of data bits are carried on each of a plurality of lines of thevideo signal; each line carries markers to define the beginning and endof the line; and when decoding the video signal, missing data bits on aline are replaced by a predetermined sequence of bits, and each saidsequence of bits is detected by an error detector and reconstituted bythe original bits by an error correction process.

Preferably, said predetermined sequence of bits comprises a string ofzero's or a string of one's.

Preferably, said decoding means comprises a counter which is reset byeach transition edge of incoming data and provides a count signal afterone-half of the duration of one data bit and thereafter at a periodequal to the duration of one bit until being reset, the count signalbeing used to detect a current data bit.

A system as above may include means for generating a display signal todisplay identification data of a current file of which the data is beingtransferred between a computer and a video recorder/player.

In use, the data of such a display signal is preferably visible whenplaying back a tape via a TV or monitor connected to the videorecorder/player.

The invention extends to a combination of a computer and/or a videorecorder/player together with a data transfer system according to any ofthe preceding aspects of the invention.

Preferably, the data transfer system is arranged to back up data from ahard disk of the computer to the video recorder/player, and to restoredata from the video recorder/player to the hard disk of the computer.

For a better understanding of the invention, and to show how embodimentsof the same may be carried into effect, reference will now be made, byway of example, to the accompanying diagrammatic drawings, in which:

BRIEF DESCRIPTION OF THE DRAWING(S)

FIG. 1 is a schematic diagram of data backup system comprising a videointerface card connected between a PC and a video recorder;

FIG. 2 is a functional block diagram of the interface card;

FIG. 3 is a functional block diagram to illustrate operation of the PC;

FIG. 4 is a block diagram of one example of a sync generator circuit;

FIG. 5 is a block diagram of one example of a buffer and serial/parallelconverter;

FIG. 6 shows a video tape and illustrates diagrammatically theinterleaving of data thereon;

FIG. 7 is a diagram to illustrate in more detail a data interleavingprocess;

FIG. 8 illustrates a television and VCR with file data display;

FIG. 9 is a waveform timing diagram illustrating a data writingoperation;

FIG. 10 is a waveform diagram illustrating frame sync pulse generation;

FIG. 11 is a waveform diagram illustrating frame sync pulses;

FIG. 12 is a flow diagram illustrating frame sync pulse decoding;

FIG. 13 is a circuit diagram of a sync and data separator;

FIG. 14 is a circuit diagram of part of an NRZ decoder;

FIG. 15 is a circuit diagram of an NRZ decoder;

FIG. 16 is a waveform timing diagram illustrating operation of the NRZdecoder;

FIG. 17 is a waveform timing diagram illustrating a data transferoperation utilising DMA (direct memory access); and

FIG. 18 illustrates an example of line code sequences.

DETAILED DESCRIPTION OF THE INVENTION

The data backup system that is shown in FIG. 1 comprises a PC 1 which isprovided with a video interfaced card 2, which in turn is connected to avideo cassette recorder (VCR) 3. Data from the PC passes through theinterface 2 to the VCR 3, where it is recorded on tape (or otherrecording medium). Data replayed from the tape passes from the VCR 3 tothe interface 2, and from there into the PC 1.

The interface 2 is shown in more detail in FIG. 2. At one end, itconnects with a PC interface 101, which makes all of the necessaryconnections to the PC 1. Connected to the PC interface 101 are a switchblock 202, a timing circuit 203, a sync separator 204, a sync generator205 and a buffer and serial/parallel converter 206. A data coder/decoder207 is connected to the timing circuit 203, the sync separator 204 andthe buffer and serial/parallel converter 206. A mixer 208 is connectedto receive signals from the sync generator 205 and the datacoder/decoder 207, and to supply a video out signal to the videorecorder 3. The sync separator 204 is arranged to receive a video insignal from the video recorder 3.

The block diagram of FIG. 3 illustrates functions that are performed bythe PC, in co-operation with the video interface 2. Briefly, under thecontrol of a program, the specification of the PC is assessed in step102, and the results of the assessment are used in a timing step 103.Alternatively, the user can directly set the timing parameters via thecomputer keyboard. Data from a disk 104 of the PC is subject to errorcorrection coding in step 105. The error correction coding step isprogrammable to enable different error rates to be accommodated.Programming is controlled by a step 107 or by user set parameters. Aftera data rate adjustment step 106, data is fed to the VCR 3, via the PCinterface 101 and the video interface 2. The data is read back from theVCR 3, and the data and error rates are assessed in step 107 or by userentered parameters, in response to which the data rate is adjusted instep 106.

Data received from the VCR 3 via the video interface 2 and PC interface101 is fed to the disk 104, after an error detection and correction step108. Both error correction and error detection can be carried out withreference to respective look up tables 109, 110.

In summary, the rate of transfer of data between the PC and the VCR viathe video interface 2 can be set in accordance with the characteristicsof both the PC and the VCR, to achieve the maximum acceptable transferrate, the characteristics being determined in the steps as mentionedabove.

The video recorder/player can be readily characterised by recording atest pattern that incorporates data transfer utilising data lines set todifferent transfer rates and differing error correction codes. Duringplayback, the lines that pass framing and error correction processeswill define suitable operating parameters.

Examples of the sync generator 205 and buffer and serial/parallelconverter 206 of the video interface card are shown in more detail inFIGS. 4 and 5.

The above described PC backup interface card 2 and associated softwareallow the PC to be interfaced to a domestic video recorder equippedwith, for example, a SCART interface. The PC backup system enables thecontents of any or all files on the personal computer hard disk 104 tobe stored on and retrieved from a standard video tape. Two PC I/O portsare utilized for the transfer of data (port A) and the control/status ofinterface card registers (port B). The interface card 2 has the form ofa standard PC expansion card.

The PC backup interface card 2 is electrically and physically compatiblewith the PC ISA standard for peripheral expansion cards. Connection tothe video signal is via a SCART type connector on the rear edge of theexpansion card accessed through an aperture in a metal end plate. Videoimpedance and drive preferably conforms to SCART standard EN50-049 (BS6552:1984), with 75 ohm termination (also known as ‘Peri-tel’ or‘Euroconnector’).

In the switch block 202, jumpers J2-J6 change the I/O port address, andthis avoids conflict with other expansion cards. Thirty two selectableaddress blocks are available from 300H to 31FH, selected in incrementsof two.

EXAMPLE

J2 J3 J4 J5 J6 Address

off off off off off 300-301H Port A 300H Port B 301H

on off off off off 302-303H Port A 302H Port B 303H

off on off off off 304-305H Port A 304H Port B 305H etc

In use of the illustrated back up system, data from the PC issuperimposed on a standard video signal, so that the data bits appear onthat portion of the video signal where luminance information wouldnormally appear. The rate at which the data is transferred depends uponthe rate at which both the PC and the VCR can transmit and store datawithin acceptable error limits, and the system is adapted to adjust therate of data transfer in accordance with those characteristics, asmentioned above. In the illustrated embodiment of the invention, thenumber of bits to be stored in each line of video signal may be selectedas either 40 or 88.

A control bit in port B sets the number of bits per line to 40 or 88, byselecting a PC Bus 14.31818 MHz clock or dividing it by two. Data rateat 40 bits per line is 625 Kbit/sec and at 88 bits per line is 1.378Mbit/sec. The time required to transfer 200 Mbyte of un-coded data is19.39 minutes or 38.78 minutes (19.39×2) for error correction coded dataassuming no compression. The time for interleaved, error coded andcompressed data is also 38.78 minutes (19.39×2×2/2).

To reduce the effects of drop out on video recording tape, the data maybe recorded on the tape in interleaved blocks. This is illustrateddiagrammatically in FIG. 6. As may be seen, data blocks n and n+1 arerecorded sequentially on the tape, and then repeated. They are thenfollowed by data blocks n+2 and n+3, which are likewise repeated.

In the example illustrated in FIG. 7, the disk 104 of the PC 1 writes toa memory buffer 120 for 40 msec periods, during each of which it fillsthe buffer with 44 kB of data. This represents a disk I/O rate of 1.1MB/sec. The tape I/O rate is 8 times slower than the disk I/O rate.Therefore, between each disk read operation, a write operation from thememory buffer 120 to the tape is carried out, during which 8 frames ofdata are written, each comprising 500 lines of 88 bits. This takes 320msec. The memory buffer 120 may comprise part of the internal RAM of thePC 1, and each data write operation to each line of the video signal maybe by direct memory access (DMA) transfer. In between each disk readoperation of 40 msec, the PC has a period of 320 msec in which it may beemployed on other tasks.

The PC preferably interleaves software processes consisting of disk I/O,data processing and interface communication.

Preferably, the data coder/decoder 207 of the video interface 2 decodesfile identification data from the PC 1, and encodes it in standard videoform to occupy some of the lines of each frame. In this way, when thedata is being either written to or read from the tape, a visual display301 of the file identification data may appear on a monitor 302 (orother display means) associated with the VCR 3, as illustrated in FIG.8.

Referring to FIGS. 9 and 10, the interface card 2 is required togenerate and detect line sync pulses, each pulse being characterized bya signal level of 0 volts and of 4.7 μs duration +/−0.1 μs.

An eight-bit clock preamble sequence is used to synchronize the samplingclock of an NRZ decoder during playback. During the back porch period,the PC software will write to port A D0-D7 the clock preamble data byte.Immediately following the back porch period, the eight bit preamble isoutput in serial form to the video output. A shift register loaded fromthe internal data buffer could be utilized but, regardless of the methodused, the data register must be free to accept a new data byte duringserial output. The signal voltage should rise to 1.0 volts for a data 1and fall to 0.3 volts for a data 0. Each bit interval should be either0.558 μsec or 1.117 μs depending on the setting of the associatedcontrol bit in port B.

During the clock preamble period, the PC software writes a data byte toport A D0-D7. Immediately following the clock preamble, this data isoutput in serial form, loaded from the internal data buffer. Signalvoltages and bit timing will remain at 0.3-1.0 volts (logic 0 & logic 1)and either 0.558 μsec or 1.117 μs depending on the setting of theassociated control bit in port B. During serial output of the first databyte, a second data byte will be written to port A by the PC software.This process will continue for either 40 or 88 bits of data depending onthe position of the associated control bit in port B. Following the lastbyte of data for each line there will be a period of at least 1.55 μswhere the video signal level will be held at 0.3 volts (the so-calledfront porch period).

After each byte has been loaded into the shift register, a status flagis set on port B D2, indicating to the PC software that the interface isready to receive a new data byte. The period between data transfer ofeach data byte from the PC to the interface card will therefore be 4.47μs or 8.94 μs (0.558×8 or 1.117×8).

A larger buffer would allow the PC software to send a whole line ofvideo data each time (40 or 88 bits), enabling the software to beengaged in other functions when not sending data. This would be ofparticular advantage if achieved at zero or little incremental cost; ifa microcontroller implementation is utilized, internal RAM could be usedas the data buffer.

Referring now to FIG. 10, after 312.5 lines of video, a series of framesync pulses are required. These pulses consist of five narrow pulses of2.3 μsec, followed by five broad pulses of 27.3 μsec, followed byanother five narrow pulses of 2.3 μsec. When the last pulse has beengenerated, the PC software initiates a line sync pulse, after which anormal video line follows. The timing tolerance for narrow and broadpulses is +/−0.1 μsec.

At the end of video line 310 the PC software initiates a frame syncpulse by writing a ‘1’ to port B D2. This causes the interface card togenerate the series of frame sync pulses. Similarly for the second framesync, half way through lines 623, the PC software initiates a frame syncby writing a second ‘1’ to port B D2.

One possible scheme that can generate the correct timing for the backporch, line sync and frame sync series is illustrated in FIG. 4. Linesyncs take 67 periods of the PC Bus 14.3 MHz clock, narrow pulses 33periods and broad pulses 319 periods, as illustrated in FIG. 11. Twocounters and two decoders generate the necessary timing. A signal on‘sync’ or ‘frame’ generates either a single line sync pulse or theseries of fifteen frame pulses. In addition, the circuit can also beused to time the back porch period. The two counters could utilize someof the registers that are needed for the NRZ decoder and bit counter.

Alternative schemes could be used that require the PC software toparticipate in the frame sync process, but present day PCs are unlikelyto be able to generate timing with accuracy better than +/−2.5 μsec.

In the example illustrated in FIG. 12, sync decoding of the frame syncis accomplished by the PC software; no additional hardware is required.The PC software simply times the period that a pulse stays low, in orderto determine the sync type.

Referring to FIG. 13, the composite video signal consists of both videoand line and frame sync information. Video (luminance) information isrepresented by signals that range between 0.3 and 1.0 volts. Syncinformation is coded as pulses of below 0.3 volts.

A simple level detector and single pole low pass RC filter are capableof detecting the falling edge of the start of the sync pulse. As thiscondition can only legitimately occur during a sync interval it is notnecessary to time the received sync period. A simple filter will removeany high frequency noise that may otherwise cause the signal tospuriously pulse low. The status of the sync level detector is availableat port B D0. The PC software polls the status of this port, waiting forthe start of the line sync interval. Immediately after the PC softwarehas polled an active sync status, it writes to port B D1, setting theinternal clock preamble register. When set, the preamble registerrequires the interface card to look for the clock preamble sequence.

Data is one bit quantised by a second level detector circuit, set at 0.6volts; again a simple RC filter is sufficient to remove any highfrequency noise. The level detector preferably utilizes positivefeedback to provide some degree of hysteresis around the 0.6 voltthreshold. The output of the data level detector is shifted into an 8bit shift register (possibly the same register used to generate serialvideo data), and a decoder connected to the shift register detectswhether the clock preamble has been received. On receipt of the clockpreamble, the preamble register should be reset, indicating that thenext eight bits are valid data. A single clock preamble is used for eachline of video data. The preamble also serves to synchronize the datasampling interval of the NRZ decoder, ready for the first byte of data.

As shown in FIGS. 15 and 16, the NRZ decoder consists of an XOR gate, adelay stage and a 3-bit resettable counter. The clock for the shiftregister is derived from the rising edge of the last output of thecounter. Each data edge is detected (by an XOR gate and a delay stage)and used to reset the counter. The counter is clocked at 14.31818 MHz(PC Bus) or 7.15909 MHz (PC Bus divide by 2) depending on the setting ofthe control bit in port B. The size of this counter is selected toensure that the shift register will sample the data level detector halfway through each bit interval. The counter is capable of continuing tocorrectly time half way through a data interval even if a series ofedgeless data is received (all 1's or all 0's), as the counter willnormally cycle back to a count of zero at the time that a data edgewould normally be detected.

After eight bits have been received they are transferred to a buffer(size>=1 byte) and the status of port B D1 is forced high to indicate tothe PC software that it should read the buffer. This process continuesuntil all of the data for the current line has been decoded andtransferred (40 or 88 bits)

In a preferred option, data transfer between the interface card and thePC could be accomplished under control of the PC DMA (direct memoryaccess) controller. This technique would free the PC microprocessor todeal more efficiently with disk I/O and error correction. However, thistechnique does require additional logic to generate and interpretcontrol signals DRQ and DACK, as illustrated in FIG. 17.

The PC software still generates a sync initiation signal, writing a data‘1’ to the control port (port B D0). However data transfer is controlledby the interface card generating a DMA request (DRQ), initially for theclock preamble and subsequently for data. On receiving the DRQ, the DMAcontroller takes control of the PC bus, generates a DACK signal andplaces data from the PC memory onto the bus. On receiving the DACKsignal, the interface card cancels the DRQ signal. Transfer of data fromthe PC bus to the data buffer is initiated on the rising edge of PC bussignal IOW. As with the software polled technique, this data is loadedinto a shift register for serial output.

After loading the shift register from the data register, a new DRQsignal is initiated. This is used by the DMA controller to place anotherdata byte onto the PC bus. This byte is then loaded into the interfacedata buffer for subsequent loading into the shift register. This processcontinues until all of the data for one line of video has beentransferred. The PC software re-initializes the DMA controller fortransfer of a new line of video data and sets up the PC counter/timerfor generating the correct timing interval (64 μs) between subsequentlines of video. The PC software then re-initiates a line sync signal(port B D0).

Reading the interface card and transferring data to the PC memoryrequires a similar sequence of events. The PC software looks for a linesync signal on port B D0, the PC software then writes to port B D1,setting the internal clock preamble register. On receipt of the clockpreamble, the preamble register is reset indicating that the next eightbits are valid data. This data is shifted into a shift register and,after eight bits have been received, the data byte is transferred to thedata register. On transfer, the interface card generates a DRQ signal,and the DMA controller takes control of the PC bus and generates a DACKsignal.

On receipt of the DACK signal, the interface card cancels the DRQ signaland while the IOR signal is low, places the data byte onto the PC bus.On the rising edge of the IOR signal the DMA controller transfers thedata byte to PC memory. This process is repeated for the whole line ofvideo data. The PC software then re-initializes the DMA controller andwaits for the sync active signal (port B D0) for the next line of videodata. Preferably, the interface is configured to accept multiple framesof video data from the DMA controller by configuring the interface 2 toinitiate its own line sync and data preamble using timer circuit 203.

Any of the designated bit positions for control and status bits may bechanged to suit the particular implementation, but preferably thesesignals should be present in the same status byte.

An important feature of the preferred embodiments of the invention isthat each physical line or group of physical lines that form a logicalline of data preferably comprises a preamble word to identify thebeginning of a new line, and a beginning and end marker to indicate aline count. FIG. 18 illustrates one example of code sequences thatimplement such a feature. The interface 2 knows to expect a certainnumber of bits between the beginning and end markers of each line.Should any bits be missing, the data is replaced with a string of zeros.The string of zeros indicates to the error correction system where theerror occurs, and this can then be corrected by standard errorcorrection techniques (eg Reed-Solomon) to restore the missing data. Byoperating in this way, the back up system can tolerate a certain loss ofdata if the PC 1 and interface 2 do not operate at the same speed. Thismeans that the system can operate at the maximum possible speed at whicha modest loss of data can be tolerated, which is sufficiently low as tobe capable of correction by error correction techniques.

Although in the above example the interface is described in terms of astandard PC expansion card, it is to be appreciated that it may beprovided in any other convenient manner. For example, it may be in theform of a “dongle” on a printer port of the PC 1.

The reader's attention is directed to all papers and documents which arefiled concurrently with or previous to this specification in connectionwith this application and which are open to public inspection with thisspecification, and the contents of all such papers and documents areincorporated herein by reference.

All of the features disclosed in this specification (including anyaccompanying claims, abstract and drawings), and/or all of the steps ofany method or process so disclosed, may be combined in any combination,except combinations where at least some of such features and/or stepsare mutually exclusive.

Each feature disclosed in this specification (including any accompanyingclaims, abstract and drawings), may be replaced by alternative featuresserving the same, equivalent or similar purpose, unless expressly statedotherwise. Thus, unless expressly stated otherwise, each featuredisclosed is one example only of a generic series of equivalent orsimilar features.

The invention is not restricted to the details of the foregoingembodiment(s). The invention extends to any novel one, or any novelcombination, of the features disclosed in this specification (includingany accompanying claims, abstract and drawings), or to any novel one, orany novel combination, of the steps of any method or process sodisclosed.

What is claimed is:
 1. A data transfer system for transferring databetween a computer and a video recorder/player, the system comprising:generating means for generating a video signal; coding means for codingdata received from the computer; mixing means for mixing such coded datawith said video signal to carry said data on said video signal;separating means for separating coded data from a video signal receivedfrom the video recorder/player; decoding means for decoding dataseparated by said separating means; set-able timing means forcontrolling the rate of transfer of data between the computer and thevideo recorder/player; and first ranging means for assessing datatransfer rate and associated error characteristics of a videorecorder/player including at least errors relating to lost portions orwhole lines of video, and providing a control signal or data to saidtiming means; whereby the signal from the first ranging means is used tocontrol the set-able timing means.
 2. The system according to claim 1,wherein at least part of said generating means, coding means, mixingmeans, separating means, decoding means and timing means are embodied asan interface device for cooperation with the computer.
 3. The systemaccording to claim 2, wherein said interface device comprises a PCexpansion card.
 4. The system according to claim 1, including secondranging means for assessing data transfer rate and associated errorcharacteristics of the computer, and providing a control signal or datato said timing means.
 5. The system according to claim 4, wherein saidsecond ranging means is arranged to assess CPU performance, availablestatic memory, disk capacity and disk I/O bandwidth of the computer. 6.The system according to claim 4 wherein at least part of said firstand/or second ranging means is embodied by way of a program within saidcomputer.
 7. The system according to claim 1 wherein: for the datacarried on said video signal, a predetermined number of data bits arecarried on each of a plurality of lines of video signal; each linecarries additional markers to identify each video line individually; andwhen decoding the video signal, missing data bits on a line are replacedby a predetermined sequence of bits, and each said sequence of bits isdetected by an error detector and reconstituted by the original bits byan error correction process.
 8. The system according to claim 7, whereinsaid predetermined sequence of bits comprises a string of zero's or astring of one's.
 9. The system according to claim 1, wherein saiddecoding means comprises a counter which is reset by each transitionedge of incoming data and provides a count signal after one-half of theduration of one data bit and thereafter at a period equal to theduration of one bit until being reset, the count signal being used todetect a current data bit.
 10. The system according to claim 1,including means for generating a display signal to displayidentification data of a current file of which the data is beingtransferred between the computer and the video recorder/player.
 11. Incombination, a computer and/or a video recorder/player together with adata transfer system according to claim
 1. 12. A combination accordingto claim 11, wherein the data transfer system is arranged to back updata from a hard disk of the computer to the video recorder/player, andto restore data from the video recorder/player to the hard disk of thecomputer.